More particularly, integrated circuit (IC) chips are formed with back end of the line (BEOL) metal levels. Each metal level can comprise metal wires (e.g., copper wires) that fill trenches with a layer of interlayer dielectric (ILD) material. Typically, at each metal level, the metal wires and adjacent ILD material will be capped with a dielectric capping layer (e.g., a silicon nitride capping layer), which minimizes electromigration (EM) and functions as an etch stop layer during formation of upper metal levels. In any case, these metal wires can function as interconnects, which provide electrical connections to on-chip devices (e.g., through vias and/or other metal wires) and/or to off-chip devices (e.g., through vias, other metal wires and/or input/output pins). Additionally, these metal wires can function as passive devices, such as inductors or resistors, or components thereof. Recently, passive devices with very thick metal wires (e.g., metal wires with a height that is greater than 2 μm, metal wires with a height that is greater than 3 μm, etc.) have been incorporated into IC chip designs. Unfortunately, the resulting IC chips tend to exhibit a relatively high rate of occurrence of delamination of the metal wires from the dielectric capping layer above and, thereby exhibit a relatively high fail rate due to opens and other structural defects resulting from the delamination. Thus, there is a need in the art for a BEOL metal level formation method that can provide relatively thick metal wires without a corresponding increase in the rate of occurrence for delamination.